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https://github.com/sedhossein/verilog-bcd-counter-jk-flip-flop
this source is Commercial bcd counter that built with Jk flip-flop in verilog
https://github.com/sedhossein/verilog-bcd-counter-jk-flip-flop
bcd counter flip-flop logic verilog
Last synced: about 6 hours ago
JSON representation
this source is Commercial bcd counter that built with Jk flip-flop in verilog
- Host: GitHub
- URL: https://github.com/sedhossein/verilog-bcd-counter-jk-flip-flop
- Owner: sedhossein
- Created: 2018-05-29T10:55:10.000Z (over 6 years ago)
- Default Branch: master
- Last Pushed: 2018-05-29T11:25:47.000Z (over 6 years ago)
- Last Synced: 2023-03-01T15:56:23.911Z (over 1 year ago)
- Topics: bcd, counter, flip-flop, logic, verilog
- Language: Verilog
- Homepage:
- Size: 247 KB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 0