https://github.com/sedhossein/verilog-bcd-counter-jk-flip-flop

this source is Commercial bcd counter that built with Jk flip-flop in verilog
https://github.com/sedhossein/verilog-bcd-counter-jk-flip-flop

bcd counter flip-flop logic verilog

Last synced: 2 months ago
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this source is Commercial bcd counter that built with Jk flip-flop in verilog

• Host: GitHub
• URL: https://github.com/sedhossein/verilog-bcd-counter-jk-flip-flop
• Owner: sedhossein
• Created: 2018-05-29T10:55:10.000Z (almost 7 years ago)
• Default Branch: master
• Last Pushed: 2018-05-29T11:25:47.000Z (almost 7 years ago)
• Last Synced: 2025-01-17T14:55:30.516Z (4 months ago)
• Topics: bcd, counter, flip-flop, logic, verilog
• Language: Verilog
• Homepage:
• Size: 247 KB
• Stars: 2
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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# verilog-bcd-counter-jk-flip-flop

this source is  Commercial bcd counter that built with JK flip-flop in verilog 

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![alt text](https://github.com/sedhossein/verilog-bcd-counter-jk-flip-flop/blob/master/test%20bench%20picture.png)