https://github.com/seldridge/chisel-separable

Separable compilation experiments in Chisel
https://github.com/seldridge/chisel-separable

Last synced: 2 months ago
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Separable compilation experiments in Chisel

• Host: GitHub
• URL: https://github.com/seldridge/chisel-separable
• Owner: seldridge
• License: apache-2.0
• Archived: true
• Created: 2022-09-23T03:27:41.000Z (about 2 years ago)
• Default Branch: main
• Last Pushed: 2023-04-25T20:02:11.000Z (over 1 year ago)
• Last Synced: 2024-06-15T22:33:33.865Z (4 months ago)
• Language: Scala
• Size: 131 KB
• Stars: 1
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
**This repository is read-only as most of its contents were upstreamed to Chisel

in https://github.com/chipsalliance/chisel/pull/3199.  Please direct

improvements to upstream Chisel.**

This repository contains experimental software that enables separable

compilation in Chisel.

This repository seeks to answer questions related to:

1. What is the _interface_ between separately compiled Chisel modules?

2. How to define a stable port-level interface between Chisel modules?

3. How can information, other than ports, be included in an interface?

4. What information can be passed between separable compilation units?

5. How can information that requires an interface implementation be described

   and communicated?

6. What software patterns are applicable to this problem?