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https://github.com/seldridge/chisel-tracing
https://github.com/seldridge/chisel-tracing
Last synced: about 1 month ago
JSON representation
- Host: GitHub
- URL: https://github.com/seldridge/chisel-tracing
- Owner: seldridge
- Created: 2023-01-20T18:52:28.000Z (almost 2 years ago)
- Default Branch: main
- Last Pushed: 2023-01-25T18:03:16.000Z (almost 2 years ago)
- Last Synced: 2024-10-19T08:18:35.866Z (2 months ago)
- Language: Scala
- Size: 2.93 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 1
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Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
Small project that shows different interesting problems related to tracing Verilog back to Chisel definitions.