https://github.com/seldridge/verilog_tex

Document and example code for introductory (and not so introductory) Verilog
https://github.com/seldridge/verilog_tex

Last synced: about 1 month ago
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Document and example code for introductory (and not so introductory) Verilog

• Host: GitHub
• URL: https://github.com/seldridge/verilog_tex
• Owner: seldridge
• Created: 2012-09-19T23:38:07.000Z (over 12 years ago)
• Default Branch: master
• Last Pushed: 2012-09-20T00:02:52.000Z (over 12 years ago)
• Last Synced: 2024-10-19T08:18:31.498Z (2 months ago)
• Language: TeX
• Size: 102 KB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README

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README

        
verilog_tex repo

Zafar M. Takhirov ([email protected])

Schuyler Eldridge ([email protected])

Boston University 2012

The intent of verilog.tex and the additional example code is to

provide a single resource for students in basic and advanced logic

design and computer architecture courses utilizing the Verilog HDL.