https://github.com/semify-eda/tristan
https://github.com/semify-eda/tristan
Last synced: 2 months ago
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- Host: GitHub
- URL: https://github.com/semify-eda/tristan
- Owner: semify-eda
- Created: 2023-04-03T12:38:31.000Z (about 3 years ago)
- Default Branch: main
- Last Pushed: 2026-03-17T14:47:41.000Z (3 months ago)
- Last Synced: 2026-03-18T00:59:30.698Z (3 months ago)
- Language: SystemVerilog
- Size: 29.6 MB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 6
-
Metadata Files:
- Readme: README.md
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README
# Tristan — RISC-V Subsystem
This directory contains the CV32E40X RISC-V core and all custom extensions.
## Setup
### Simulation tools (Verilator)
Verilator is installed as part of the SmartWave toolchain:
```bash
./setup/install.sh # from repo root — installs Verilator + Python
```
Source the environment to set `$WFG_ROOT` and `$TRISTAN_ROOT`:
```bash
source sourceme.bash # from repo root
```
### RISC-V Compiler Toolchain
To compile firmware you need the RISC-V GNU toolchain configured for `rv32ia`:
```bash
git clone https://github.com/riscv-collab/riscv-gnu-toolchain
cd riscv-gnu-toolchain
sudo ./configure --prefix=/opt/riscv --with-arch=rv32ia
make
```
Add `/opt/riscv/bin` and `/opt/riscv/riscv32-unknown-elf/bin` to your `PATH`.
## Instructions
For cv32a60x core, a patch is needed, so vivado can read the file. We cannot push this to the submodule, as we use the official CVA6 repo directly instead of our own fork.
cp core/csr_regfile_patched.sv core/cv6/core/csr_regfile.sv
Compile firmware:
make firmware
Run the simulation (Verilator):
cd design/tristan
make
Run a specific test:
make TESTCASE=
Clean simulation artifacts:
make clean
## Simulation
Top-level testbench for tristan is under `core/testbench` and simulation is ran in the root of the tristan module with:
make
Each custom module has its own `sim/` directory:
| Module | Directory |
|---|---|
| Co-processor (shifter) | `core/custom/coproc/sim/` |
| OBI→Wishbone bridge | `core/custom/obi_wb_bridge/sim/` |
| Wishbone RAM interface | `core/custom/wb_ram_interface/sim/` |
Run any of these the same way:
cd core/custom//sim
make