https://github.com/septiscom/systemverilogcircuits
https://github.com/septiscom/systemverilogcircuits
Last synced: 5 months ago
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- Host: GitHub
- URL: https://github.com/septiscom/systemverilogcircuits
- Owner: Septiscom
- Created: 2024-12-23T23:13:52.000Z (over 1 year ago)
- Default Branch: Intermediate-Modules-and-Constructs
- Last Pushed: 2025-01-14T12:44:48.000Z (over 1 year ago)
- Last Synced: 2025-05-18T12:36:17.203Z (about 1 year ago)
- Language: SystemVerilog
- Size: 15.6 KB
- Stars: 1
- Watchers: 1
- Forks: 1
- Open Issues: 0
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Metadata Files: