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https://github.com/sequencer/tilelink
https://github.com/sequencer/tilelink
Last synced: 3 months ago
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- Host: GitHub
- URL: https://github.com/sequencer/tilelink
- Owner: sequencer
- Created: 2021-10-29T20:59:15.000Z (about 3 years ago)
- Default Branch: master
- Last Pushed: 2023-08-10T16:06:00.000Z (over 1 year ago)
- Last Synced: 2024-08-03T01:39:20.485Z (6 months ago)
- Language: Scala
- Size: 20.5 KB
- Stars: 4
- Watchers: 4
- Forks: 2
- Open Issues: 0
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Metadata Files:
- Readme: readme.md
Awesome Lists containing this project
README
# TileLink
Chisel library of TileLink, providing TileLink interconnect datatype declaration.
## Pending PRs
Philosophy of this repository is **fast break and fast fix**.
This repository always tracks remote developing branches, it may need some patches to work, `make patch` will append below in sequence:
rocket-chip https://github.com/chipsalliance/rocket-chip/pull/2968
rocket-chip https://github.com/chipsalliance/rocket-chip/pull/3013
## TODO
### BUSIP
These IPs will be ported from RocketChip, but work with the D/I of Chisel3.
### Diplomatic
It defines the diplomatic busip, which can be used for diplomatic connection.