https://github.com/serhaturtis/dd-ltc2311-16
IP Module For LTC2311 ADC
https://github.com/serhaturtis/dd-ltc2311-16
adc digitaldesign fpga ltc2311 systemverilog
Last synced: 3 months ago
JSON representation
IP Module For LTC2311 ADC
- Host: GitHub
- URL: https://github.com/serhaturtis/dd-ltc2311-16
- Owner: serhaturtis
- License: mit
- Created: 2023-06-12T18:57:57.000Z (almost 2 years ago)
- Default Branch: master
- Last Pushed: 2024-01-23T18:12:19.000Z (over 1 year ago)
- Last Synced: 2024-01-23T20:28:43.686Z (over 1 year ago)
- Topics: adc, digitaldesign, fpga, ltc2311, systemverilog
- Language: SystemVerilog
- Homepage:
- Size: 414 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0