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https://github.com/shabbygaybar/verilogamslib

Library of Verilog-AMS models
https://github.com/shabbygaybar/verilogamslib

cadence-spectre hardware-description-language verilog-a

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Library of Verilog-AMS models

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# Verilog-AMS Library

This repository contains a collection of Verilog-AMS models for various electronic components and systems. The models are designed to be used in circuit simulation tools that support the Verilog-AMS language.

## Models
- `amp_dynamic`: A dynamic amplifier model.
- `dff_rsn`: A D flip-flop with reset and set functionality.
- `comparator_dynamic`: A dynamic comparator model.
- `tah_ideal`: An ideal track and hold model.
- `adc_16bit_ideal`: An ideal 16-bit analog-to-digital converter.
- `dac_16bit_ideal`: An ideal 16-bit digital-to-analog converter.
- `vcdl`: A voltage-controlled delay line model.

## License

This mod is under [MIT LICENSE](LICENSE).