https://github.com/shabbygaybar/verilogamslib
Library of Verilog-AMS models
https://github.com/shabbygaybar/verilogamslib
cadence-spectre hardware-description-language verilog-a
Last synced: 4 months ago
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Library of Verilog-AMS models
- Host: GitHub
- URL: https://github.com/shabbygaybar/verilogamslib
- Owner: ShabbyGayBar
- License: mit
- Created: 2025-02-26T03:03:04.000Z (4 months ago)
- Default Branch: master
- Last Pushed: 2025-02-26T03:28:34.000Z (4 months ago)
- Last Synced: 2025-02-26T04:25:56.071Z (4 months ago)
- Topics: cadence-spectre, hardware-description-language, verilog-a
- Homepage:
- Size: 3.91 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# Verilog-AMS Library
This repository contains a collection of Verilog-AMS models for various electronic components and systems. The models are designed to be used in circuit simulation tools that support the Verilog-AMS language.
## Models
- `amp_dynamic`: A dynamic amplifier model.
- `dff_rsn`: A D flip-flop with reset and set functionality.
- `comparator_dynamic`: A dynamic comparator model.
- `tah_ideal`: An ideal track and hold model.
- `adc_16bit_ideal`: An ideal 16-bit analog-to-digital converter.
- `dac_16bit_ideal`: An ideal 16-bit digital-to-analog converter.
- `vcdl`: A voltage-controlled delay line model.
## License
This mod is under [MIT LICENSE](LICENSE).