https://github.com/shalan/ms_qspi_xip_cache

AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP
https://github.com/shalan/ms_qspi_xip_cache

ahb-lite asic ip qspi qspi-flash sky130 verilog

Last synced: 3 months ago
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AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP

• Host: GitHub
• URL: https://github.com/shalan/ms_qspi_xip_cache
• Owner: shalan
• License: apache-2.0
• Created: 2023-08-17T13:14:52.000Z (almost 2 years ago)
• Default Branch: main
• Last Pushed: 2023-11-09T14:41:23.000Z (over 1 year ago)
• Last Synced: 2023-11-09T15:41:04.890Z (over 1 year ago)
• Topics: ahb-lite, asic, ip, qspi, qspi-flash, sky130, verilog
• Language: Verilog
• Homepage:
• Size: 522 KB
• Stars: 3
• Watchers: 2
• Forks: 2
• Open Issues: 3
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# MS_QSPI_XIP_CACHE

Quad I/O SPI Flash memory controller with support for:

- AHB lite interface

- Execute in Place (XiP)

- Nx16 Direct-Mapped Cache (default: N=32).

Intended to be used with SoCs that have no on-chip flash memory. 

## Todo:

 - [ ] support for WB bus

 - [ ] Support cache configurations other than 16 bytes per line

## Performance

The following data is obtained using Sky130 HD library

| Configuration | # of Cells (K) | Delay (ns) | Idyn (mA/MHz) | Is (nA) | 

|---------------|----------------|------------|--------------------------|--------------------|

| 16x16 | 7.2 | 12 | 0.0625 | 20 |

| 32x16 | 14.3 | 17  | 0.126 | 39.5 |