https://github.com/shilpakancharla/learning-vhdl

templates for vhdl
https://github.com/shilpakancharla/learning-vhdl

Last synced: about 2 months ago
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templates for vhdl

• Host: GitHub
• URL: https://github.com/shilpakancharla/learning-vhdl
• Owner: shilpakancharla
• Created: 2021-06-17T20:42:59.000Z (almost 4 years ago)
• Default Branch: main
• Last Pushed: 2021-06-24T14:01:10.000Z (almost 4 years ago)
• Last Synced: 2025-01-19T22:49:26.292Z (3 months ago)
• Language: VHDL
• Size: 7.81 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# learning-vhdl

* Recall entity-architecture pair.

* Instead of a parameter list, we have a port list because we are working with hardware.

* `halfAdder` diagram

![alt text](https://user-images.githubusercontent.com/31664851/122470273-da038680-cf8b-11eb-9161-0c658aabcb43.png)

* 4-bit Adder

![alt text](https://user-images.githubusercontent.com/31664851/122472030-05877080-cf8e-11eb-8bb8-59a4005b9f9f.png)