https://github.com/shiva9361/simple_processor

Verilog implementation of a RISC-V processor with a subset of RISC-V instructions
https://github.com/shiva9361/simple_processor

risc-v ver

Last synced: 3 months ago
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Verilog implementation of a RISC-V processor with a subset of RISC-V instructions

• Host: GitHub
• URL: https://github.com/shiva9361/simple_processor
• Owner: Shiva9361
• License: mit
• Created: 2024-04-19T18:52:18.000Z (about 1 year ago)
• Default Branch: main
• Last Pushed: 2024-05-18T07:49:58.000Z (about 1 year ago)
• Last Synced: 2025-01-01T11:25:49.689Z (5 months ago)
• Topics: risc-v, ver
• Language: Verilog
• Homepage:
• Size: 13.7 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: readme.md
  • License: LICENSE

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README

        
# RISC V based single cycle processor in verilog

Made mostly using combinational logic

The following instructtions are implemented

- add

- sub

- xor

- or

- and

- sll

- srl

- sra

- slt

- sltu

- lw

- sw