https://github.com/shreyb2091/cse-bubble-processor

https://github.com/shreyb2091/cse-bubble-processor

assembly cs220 cse iitk mips processor sem-4

Last synced: 5 days ago
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• Host: GitHub
• URL: https://github.com/shreyb2091/cse-bubble-processor
• Owner: ShreyB2091
• Created: 2023-04-21T20:26:29.000Z (almost 2 years ago)
• Default Branch: master
• Last Pushed: 2023-05-11T08:20:38.000Z (almost 2 years ago)
• Last Synced: 2024-12-12T03:42:24.996Z (2 months ago)
• Topics: assembly, cs220, cse, iitk, mips, processor, sem-4
• Language: Verilog
• Homepage:
• Size: 1.41 MB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# CSE BUBBLE Processor

This is a processor made using Verilog HDL.

It was made as a part of a course project (CS220) - Computer Organization

A custom architecture set similar to MIPS was made. It consists of 3 memory modules, an ALU module and a CPU module.

It was made to perform Bubble Sort on a given a array stored in the data memory module. The machine code for the sorting algorithm is stored in the instructions memory module.

To run the processor, run ```iverilog -o cpu_tb.vvp cpu_tb.v``` to compile the program. Then run ```vvp cpu_tb.vvp``` to execute the program.