https://github.com/shsridhar-beep/svgap
Structural-validity evaluation for AI-generated RTL
https://github.com/shsridhar-beep/svgap
ai-evaluation benchmark cdc clock-domain-crossing eda hardware-verification llm llm-evaluation rdc rtl systemverilog verilog yosys
Last synced: about 14 hours ago
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Structural-validity evaluation for AI-generated RTL
- Host: GitHub
- URL: https://github.com/shsridhar-beep/svgap
- Owner: shsridhar-beep
- License: apache-2.0
- Created: 2026-07-03T02:53:26.000Z (18 days ago)
- Default Branch: main
- Last Pushed: 2026-07-03T04:57:10.000Z (18 days ago)
- Last Synced: 2026-07-03T06:27:43.603Z (18 days ago)
- Topics: ai-evaluation, benchmark, cdc, clock-domain-crossing, eda, hardware-verification, llm, llm-evaluation, rdc, rtl, systemverilog, verilog, yosys
- Language: Python
- Homepage: https://doi.org/10.5281/zenodo.21152349
- Size: 230 KB
- Stars: 0
- Watchers: 0
- Forks: 0
- Open Issues: 5