https://github.com/shuai132/dma_axis_ltc2324_16

LTC2324-16 driver for Xilinx AXI-DMA
https://github.com/shuai132/dma_axis_ltc2324_16

adi axi-dma ltc2324 verilog-hdl

Last synced: 29 days ago
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LTC2324-16 driver for Xilinx AXI-DMA

• Host: GitHub
• URL: https://github.com/shuai132/dma_axis_ltc2324_16
• Owner: shuai132
• Created: 2019-11-06T01:20:18.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2019-12-16T18:10:06.000Z (about 5 years ago)
• Last Synced: 2024-11-05T14:12:23.612Z (3 months ago)
• Topics: adi, axi-dma, ltc2324, verilog-hdl
• Language: VHDL
• Size: 12.5 MB
• Stars: 3
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# DMA_AXIS_LTC2324_16

using SDR Mode, CMOS (Reading 1 Channel per SDO)

## LTC2324_16

* 2Msps/Ch Throughput Rate

* Four Simultaneously Sampling Channels

* Guaranteed 16-Bit, No Missing Codes

* 8VP-P Differential Inputs with Wide Input Common Mode Range

* 82dB SNR (Typ) at fIN = 500kHz

* –90dB THD (Typ) at fIN = 500kHz

* Guaranteed Operation to 125°C

* Single 3.3V or 5V Supply

* Low Drift (20ppm/°C Max) 2.048V or 4.096V Internal Reference

* 1.8V to 2.5V I/O Voltages

* CMOS or LVDS SPI-Compatible Serial I/O

* Power Dissipation 40mW/Ch (Typ)

* Small 52-Pin (7mm × 8mm) QFN Package

## TIMING DIAGRAM

![](img/TIMING_DIAGRAM.png)

![](img/TIMING.png)

* CNV  

  The rising edge jitter of CNV is

  much less critical to performance. The typical pulse width

  of the CNV signal is 30ns with < 1.5ns rise and fall times

  at a 2Msps conversion rate

* SCK  

  In DDR mode (SDR/DDR Pin 23 = OVDD),

  each input edge of SCK shifts the conversion result MSB

  first onto the SDO pins. A 55MHz external clock must be

  applied at the SCK pin to achieve 2Msps throughput using

  all four SDO1 through SDO4 outputs

## Links

* [LTC2324-16 Data Sheets](https://www.analog.com/media/en/technical-documentation/data-sheets/232416f.pdf)