https://github.com/shuregg/ialu-verification

Syntacore scr1 iALU verification example
https://github.com/shuregg/ialu-verification

alu cpu riscv rtl systemverilog verification

Last synced: 6 months ago
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Syntacore scr1 iALU verification example

• Host: GitHub
• URL: https://github.com/shuregg/ialu-verification
• Owner: Shuregg
• Created: 2024-02-01T18:28:10.000Z (over 1 year ago)
• Default Branch: develop_branch2
• Last Pushed: 2024-03-07T09:18:28.000Z (over 1 year ago)
• Last Synced: 2024-12-13T10:14:14.525Z (10 months ago)
• Topics: alu, cpu, riscv, rtl, systemverilog, verification
• Language: SystemVerilog
• Homepage:
• Size: 42.1 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

          
iALU's ADD and SUB operations verification and code/functional coverage

========================================================================

Code coverage:

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![report png](https://github.com/Shuregg/ialu-verification/assets/47576452/9a53cfeb-b433-4926-b971-fc28bb2bb558)

Functional coverage:

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![fcover png](https://github.com/Shuregg/ialu-verification/assets/47576452/5434d5aa-8cae-4fd3-8590-54aabd3e0543)

Check next files for more information:

code_cover_report.txt[1], 

func_cover_report.txt[2], 

general_coverage_report_details.txt[3]

[1] [https://github.com/Shuregg/ialu-verification/blob/develop/coverage_reports/code_cover_report.txt]

[2] [https://github.com/Shuregg/ialu-verification/blob/develop/coverage_reports/func_cover_report.txt]

[3] [https://github.com/Shuregg/ialu-verification/blob/develop/coverage_reports/general_coverage_report_details.txt]