https://github.com/shuregg/riscv-simple-cpu

Creating a risc-v processor
https://github.com/shuregg/riscv-simple-cpu

cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl

Last synced: 10 days ago
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Creating a risc-v processor

• Host: GitHub
• URL: https://github.com/shuregg/riscv-simple-cpu
• Owner: Shuregg
• Created: 2023-09-13T15:08:19.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2024-04-04T23:21:43.000Z (9 months ago)
• Last Synced: 2024-04-05T01:18:29.838Z (9 months ago)
• Topics: cpu, risc-v, riscv, riscv32, rtl, systemverilog, verification, verilog, verilog-hdl
• Language: SystemVerilog
• Homepage:
• Size: 4.58 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# RISC-V simple CPU

## Main characteristics

* RV32I Zicsr ISA

* Single-core single-cycle CPU

* Interruption subsystem

* Load-Store Unit (LSU)

* Control and Status Registers unit (CSR)

* Peripheral device support