https://github.com/shuregg/riscv-simple-cpu
Creating a risc-v processor
https://github.com/shuregg/riscv-simple-cpu
cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl
Last synced: 30 days ago
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Creating a risc-v processor
- Host: GitHub
- URL: https://github.com/shuregg/riscv-simple-cpu
- Owner: Shuregg
- Created: 2023-09-13T15:08:19.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2024-04-04T23:21:43.000Z (over 1 year ago)
- Last Synced: 2025-03-31T08:46:37.646Z (7 months ago)
- Topics: cpu, risc-v, riscv, riscv32, rtl, systemverilog, verification, verilog, verilog-hdl
- Language: SystemVerilog
- Homepage:
- Size: 4.58 MB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# RISC-V simple CPU
## Main characteristics
* RV32I Zicsr ISA
* Single-core single-cycle CPU
* Interruption subsystem
* Load-Store Unit (LSU)
* Control and Status Registers unit (CSR)
* Peripheral device support