https://github.com/shyamal-anadkat/wisc-sp13

CS 552 term project : functional design of a microprocessor called the WISC-SP13
https://github.com/shyamal-anadkat/wisc-sp13

cs552 hardware-designs mips-assembly processor processor-architecture verilog verilog-hdl

Last synced: about 2 months ago
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CS 552 term project : functional design of a microprocessor called the WISC-SP13

• Host: GitHub
• URL: https://github.com/shyamal-anadkat/wisc-sp13
• Owner: shyamal-anadkat
• Created: 2017-02-02T21:13:49.000Z (almost 8 years ago)
• Default Branch: master
• Last Pushed: 2017-05-14T05:42:06.000Z (over 7 years ago)
• Last Synced: 2024-10-28T19:21:20.300Z (3 months ago)
• Topics: cs552, hardware-designs, mips-assembly, processor, processor-architecture, verilog, verilog-hdl
• Language: Assembly
• Size: 148 MB
• Stars: 4
• Watchers: 2
• Forks: 6
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# WISC-SP13 

CS 552 term project : functional design of a microprocessor called the WISC-SP13


Overview and specifications can be previewed here: http://pages.cs.wisc.edu/~karu/courses/cs552/spring2017/wiki/index.php/Main/ProjectDeadlinesAndGrading