https://github.com/sifive/block-inclusivecache-sifive

https://github.com/sifive/block-inclusivecache-sifive

Last synced: 2 months ago
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• Host: GitHub
• URL: https://github.com/sifive/block-inclusivecache-sifive
• Owner: sifive
• License: apache-2.0
• Created: 2019-06-22T01:00:04.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2022-06-01T18:40:37.000Z (over 2 years ago)
• Last Synced: 2024-08-03T01:39:22.620Z (6 months ago)
• Language: Scala
• Size: 38.1 KB
• Stars: 71
• Watchers: 11
• Forks: 45
• Open Issues: 11
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# block-inclusivecache-sifive

This `block` package contains an RTL generator for creating instances of a coherent, last-level, inclusive cache.

The `InclusiveCache` controller enforces coherence among a set of caching clients

using an invalidation-based coherence policy. 

This policy is implemented using a full-map of directory bits stored with each cache block's metadata tag.

The `InclusiveCache` is a TileLink adapter;

it can be used as a drop-in replacement for Rocket-Chip's `tilelink.BroadcastHub` coherence manager.

It additionally supplies a SW-controlled interface for flusing cache blocks based on physical addresses.

The following parameters of the cache are easily `Config`-urable: 

size, ways, banking and sub-banking factors, external bandwidth, network interface buffering.

Stand-alone unit tests coming soon.