https://github.com/sifive/chisel-circt-demo
Demonstration of a project using sifive/chisel-circt
https://github.com/sifive/chisel-circt-demo
chisel circt mlir scala
Last synced: 2 months ago
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Demonstration of a project using sifive/chisel-circt
- Host: GitHub
- URL: https://github.com/sifive/chisel-circt-demo
- Owner: sifive
- License: apache-2.0
- Created: 2021-01-26T23:21:36.000Z (over 4 years ago)
- Default Branch: main
- Last Pushed: 2022-09-28T18:26:27.000Z (almost 3 years ago)
- Last Synced: 2024-04-28T01:28:18.570Z (about 1 year ago)
- Topics: chisel, circt, mlir, scala
- Language: Scala
- Homepage:
- Size: 20.5 KB
- Stars: 9
- Watchers: 6
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
**This project is no longer relevant as upstream Chisel now supports CIRCT natively. For instructions about how to use Chisel, please refer to the [Chisel website](https://chisel-lang.org).**
This repository demonstrates the [sifive/chisel-circt](https://github.com/sifive/chisel-circt) being used in a Chisel project.
The following requirements must be met:
- `sbt` available on your path
- [llvm/circt](https://github.com/llvm/circt) utilities (`firtool`) available on your path
With those available, you can then run one of two commands:
- `sbt run` to show a module compiled with the Scala FIRRTL Compiler (SFC) and the MLIR FIRRTL Compiler (MFC)
- `sbt test` to run simple checks that the output Verilog makes sense