https://github.com/sigma-logic/common-cores
Common cores for internal use under organization. Mostly oriented on Gowin Arora V family
https://github.com/sigma-logic/common-cores
fpga gowin hardware-design ip-core system-verilog verilog
Last synced: about 2 months ago
JSON representation
Common cores for internal use under organization. Mostly oriented on Gowin Arora V family
- Host: GitHub
- URL: https://github.com/sigma-logic/common-cores
- Owner: sigma-logic
- Created: 2025-01-28T10:32:19.000Z (4 months ago)
- Default Branch: main
- Last Pushed: 2025-01-30T16:28:53.000Z (4 months ago)
- Last Synced: 2025-01-30T17:31:33.012Z (4 months ago)
- Topics: fpga, gowin, hardware-design, ip-core, system-verilog, verilog
- Language: SystemVerilog
- Homepage:
- Size: 85.9 KB
- Stars: 1
- Watchers: 0
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: readme.md
Awesome Lists containing this project
README
# Common Cores
Common IP cores intended for internal use in projects under Sigma Logic organization. Mainly targeting **Gowin Arora V** FPGA chips family, but not exclusively.
# License
You are free to use IP cores with no limitations in personal projects or by including this git repository as a submodule in your project.
If you copy, edit, modify or indirectly adding contents (hdl code) of the IP cores in a public project,
please mention original [repository](https://github.com/sigma-logic/common-cores) link and the author ([repo](https://github.com/sigma-logic/common-cores) owner) in comments inside hdl code or **readme.md** file. Do not use in commertial projects.
# Cores
|Name |Description |Dev Status |Notes
|:-----------------------------------------------------------------------------------|:------------------------------------|:-------------|:--------------------------------------------|
|[WS2812](https://github.com/sigma-logic/common-cores/tree/main/cores/ws2812) |Addressable RGB led driver |New (unstable)|Supports only single LED
|[RGMII](https://github.com/sigma-logic/common-cores/tree/main/cores/rgmii) |RGMII phy level |WiP (unstable)|Network stack up to you, it's only DDR buffer
|[Simple PLL](https://github.com/sigma-logic/common-cores/tree/main/cores/simple_pll)|PLL configuration covering most needs|Stable |Just cozy PLL module
|[LVDS](https://github.com/sigma-logic/common-cores/tree/main/cores/lvds) |LVDS I/O buffers |Stable |Wrapper around ELVDS/TLVDS
---
###### [Telegram](https://t.me/limpix31), [Sigma Logic Discord Server](https://discord.gg/HPJJsenZ76)