https://github.com/siri-n-shetty/iverilog
This repository contains a series of Verilog codes for the course UE22CS251A (DDCO).
https://github.com/siri-n-shetty/iverilog
ddco pesu vcd verilog verilog-code
Last synced: about 1 month ago
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This repository contains a series of Verilog codes for the course UE22CS251A (DDCO).
- Host: GitHub
- URL: https://github.com/siri-n-shetty/iverilog
- Owner: siri-n-shetty
- Created: 2023-08-25T18:01:22.000Z (almost 3 years ago)
- Default Branch: main
- Last Pushed: 2024-11-11T04:25:08.000Z (over 1 year ago)
- Last Synced: 2024-11-11T05:26:32.523Z (over 1 year ago)
- Topics: ddco, pesu, vcd, verilog, verilog-code
- Language: Verilog
- Homepage:
- Size: 9.26 MB
- Stars: 13
- Watchers: 1
- Forks: 5
- Open Issues: 0
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Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
## UE22CS251A: Digital Design and Computer Organization Laboratory
This repository contains Verilog code and associated problem statements for each of the 8 weeks of laboratory exercises completed during the third semester as part of the course: DDCO.
### Repository Structure
The repository is organized into weekly folders. Each weekly folder contains:
* README.md: Describes the problem statements for the week.
* Verilog Files (.v): Contains the Verilog source code for the laboratory exercises.
### Contributions
Feel free to contribute by submitting issues for any bugs or improvements.
I hope this serves as a valuable resource for your learning and projects in DDCO.