https://github.com/skpro-glitch/multi-bit-comparator

Variations of a multi-bit generalized comparator for different area and timing.
https://github.com/skpro-glitch/multi-bit-comparator

altera-quartus comparator digital-design fpga fpga-programming logic-circuit low-power power-gating register-transfer-level rtl rtl-design serial-port serialization verilog-hdl vlsi vlsi-design xilinx-vivado

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Variations of a multi-bit generalized comparator for different area and timing.

• Host: GitHub
• URL: https://github.com/skpro-glitch/multi-bit-comparator
• Owner: SKpro-glitch
• Created: 2025-01-16T05:12:25.000Z (3 months ago)
• Default Branch: main
• Last Pushed: 2025-01-16T10:58:23.000Z (3 months ago)
• Last Synced: 2025-01-29T10:35:59.942Z (3 months ago)
• Topics: altera-quartus, comparator, digital-design, fpga, fpga-programming, logic-circuit, low-power, power-gating, register-transfer-level, rtl, rtl-design, serial-port, serialization, verilog-hdl, vlsi, vlsi-design, xilinx-vivado
• Language: Verilog
• Homepage:
• Size: 31.3 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Multi-Bit-Comparator

**Author:** Soham Kapur

 

**Description:** Variations of a generalized multi-bit/magnitude comparator with trade-offs among timing and area.

**Tools Used:** Verilog HDL, Xilinx Vivado, Altera Quartus

 

**Concepts Used:** Clock gating, Power gating, Area-Power-Timing trade-off, Comparator

 

**Device Simulated:** Cyclone IV E: EP4CE115F29C7

 

**Multi Bit Comparator with Power Gating:** 4-bit Comparator

![image](https://github.com/user-attachments/assets/83017971-f21f-4b3d-ba02-daf77f90432b)

 

**Single Bit Comparator with Power Gating:** Fmax = 103.69 MHz

![image](https://github.com/user-attachments/assets/ba54a9f9-df3f-4b8d-9bd7-729253db7038)

 

**Serialized Multi Bit Comparator:** Fmax = 118.88 MHz

![image](https://github.com/user-attachments/assets/fffdd3b8-c5a5-40d7-b859-9f90e69871de)