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https://github.com/socxin/bl602

L3 R3：bouffalolab 192MHz RISC-V Wi-Fi/BLE SoC (BL602/ BL604)
https://github.com/socxin/bl602

ble bouffalolab qitas risc-v soc wifi

Last synced: 20 days ago
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L3 R3：bouffalolab 192MHz RISC-V Wi-Fi/BLE SoC (BL602/ BL604)

Host: GitHub
URL: https://github.com/socxin/bl602
Owner: SoCXin
Created: 2023-01-30T02:37:41.000Z (almost 2 years ago)
Default Branch: main
Last Pushed: 2023-01-30T02:55:50.000Z (almost 2 years ago)
Last Synced: 2024-11-05T10:33:40.060Z (2 months ago)
Topics: ble, bouffalolab, qitas, risc-v, soc, wifi
Homepage:
Size: 1.09 MB
Stars: 1
Watchers: 0
Forks: 0
Open Issues: 0
Metadata Files:
- Readme: README.md
- Funding: .github/FUNDING.yml

Awesome Lists containing this project

README

        # [BL602](https://doc.soc.xin/BL602)

* [bouffalolab](http://www.bouffalolab.com/): [RISC-V](https://github.com/SoCXin/RISC-V)

* [L3R3](https://github.com/SoCXin/Level): 192MHz , [￥7.03](https://item.szlcsc.com/3078664.html)

## [简介](https://github.com/SoCXin/BL602/wiki)

[BL602](https://www.bouffalolab.com/product/?type=list&category=13) 是一款 Wi-Fi + BLE 组合的芯片组，用于低功耗和高性能应用开发。无线子系统包含 2.4G 无线电，Wi-Fi

802.11b/g/n 和 BLE 5.0 基带/MAC 设计。微控制器子系统包含一个低功耗的 32 位 RISC CPU，高速缓存和存储器。电源管理单元控制低功耗模式。此外，还支持各种安全性能。

外围接口包括 SDIO，SPI，UART，I2C，IR remote，PWM，ADC，DAC，PIR 和 GPIO。

### 关键参数

* 192MHz RISC-V Core (带FPU, 1.46 DMIPS/MHz, 3.1 CoreMark/MHz)

* 276KB SRAM

* 802.11 b/g/n 1T1R 模式，支持 20 MHz，数据速率高达 72.2 Mbps

* 2x CMP

* 2Msps ADC + 512Ksps DAC

* 1 路 SDIO2.0 从机

* I2C + SPI + 2x UART

## [资源收录](https://github.com/SoCXin)

* [参考资源](src/)

* [参考文档](docs/)

* [参考工程](project/)

## [选型建议](https://github.com/SoCXin/BL602)

[BL602](https://item.szlcsc.com/3078664.html) 相对 [ESP32-C3](https://github.com/SoCXin/ESP32C3) 在WiFi带宽和SDK资源上显劣势，也支持BLE共存，但是在模拟性能和功耗上有优势，都是走开源生态路线，非常推荐应用于物联网产品中。

[官方资源下载](https://dev.bouffalolab.com/document?chip=BL602%2F604)和[在线文档](https://dev.bouffalolab.com/media/doc/602/open/datasheet/zh/html/index.html)

## [www.SoC.xin](http://www.SoC.Xin)