https://github.com/socxin/ch32v103

L2 R2：WCH RISC-V MCU(CH32V103)
https://github.com/socxin/ch32v103

mcu qitas risc-v risc-v3a riscv usb-host wch

Last synced: about 2 months ago
JSON representation

L2 R2：WCH RISC-V MCU(CH32V103)

• Host: GitHub
• URL: https://github.com/socxin/ch32v103
• Owner: SoCXin
• Created: 2019-05-04T02:28:29.000Z (about 6 years ago)
• Default Branch: master
• Last Pushed: 2022-07-10T14:35:21.000Z (almost 3 years ago)
• Last Synced: 2025-03-20T17:01:58.601Z (2 months ago)
• Topics: mcu, qitas, risc-v, risc-v3a, riscv, usb-host, wch
• Language: C
• Homepage: https://doc.soc.xin/CH32V103
• Size: 13.4 MB
• Stars: 7
• Watchers: 1
• Forks: 4
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Funding: .github/FUNDING.yml

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