https://github.com/socxin/ch569
L2 R6: WCH 120MHz RISC-V3A USB3.0 SoC (CH569)
https://github.com/socxin/ch569
aes emmc ethernet hspi qfn qitas risc-v risc-v3a serdes sm4 usb3 wch
Last synced: about 1 year ago
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L2 R6: WCH 120MHz RISC-V3A USB3.0 SoC (CH569)
- Host: GitHub
- URL: https://github.com/socxin/ch569
- Owner: SoCXin
- Created: 2019-02-21T08:48:53.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2023-02-18T12:05:06.000Z (over 3 years ago)
- Last Synced: 2025-03-20T17:01:44.909Z (about 1 year ago)
- Topics: aes, emmc, ethernet, hspi, qfn, qitas, risc-v, risc-v3a, serdes, sm4, usb3, wch
- Language: C
- Homepage: https://doc.soc.xin/CH569
- Size: 11.5 MB
- Stars: 16
- Watchers: 2
- Forks: 6
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- Funding: .github/FUNDING.yml