https://github.com/soham9284/vedic-multiplier-using-cmos-design
Transistor-level design, simulation, and layout of a 2-bit Vedic multiplier using CMOS technology with netlist and layout optimization.
https://github.com/soham9284/vedic-multiplier-using-cmos-design
cmos microwind ngspice
Last synced: about 1 month ago
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Transistor-level design, simulation, and layout of a 2-bit Vedic multiplier using CMOS technology with netlist and layout optimization.
- Host: GitHub
- URL: https://github.com/soham9284/vedic-multiplier-using-cmos-design
- Owner: soham9284
- License: mit
- Created: 2025-04-14T10:49:14.000Z (about 1 month ago)
- Default Branch: main
- Last Pushed: 2025-04-14T11:31:56.000Z (about 1 month ago)
- Last Synced: 2025-04-14T12:28:14.912Z (about 1 month ago)
- Topics: cmos, microwind, ngspice
- Homepage:
- Size: 13.7 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE
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README
**Project Overview**
The 2-bit Vedic multiplier design presents a CMOS-based digital circuit that multiplies binaries based on the Vedic algorithm "Urdhva Tiryagbhyam". The circuit takes two 2-bit binary inputs and has a 4-bit product output. The design was accomplished with all NMOS and PMOS transistors without employing pre-defined gates of logic, thus providing complete power, performance, and area control.
Simple logic operations like AND, XOR were designed at the transistor level and combined based on the Vedic principles of multiplication, which simplify the process of multiplication by employing vertical and crosswise partial product generation. The final design was simulated to verify its correctness and optimized for low power usage and good layout, thereby proving the efficiency of Vedic algorithms in the area of digital design.
**Objectives**
1. Design a 2-bit CMOS Vedic multiplier based on the “Urdhva-Tiryagbhyam” algorithm.
2. Generate a 4-bit product output from two 2-bit binary inputs.
3. Implement the entire circuit using only NMOS and PMOS transistors.
4. Verify the circuit’s functional correctness through simulation in Microwind.
5. Write a SPICE-compatible netlist to describe transistor-level connectivity.
6. Develop an optimized layout with focus on power, performance, and area for potential fabrication.
**Design Description**
1. The circuit takes two 2-bit binary inputs, A (A1A0) and B (B1B0), and performs multiplication based on the Vedic algorithm "Urdhva-Tiryagbhyam."
2. For the multiplication process, the circuit generates partial products by performing bitwise AND, XOR operations on the corresponding bits of A and B.
3. The vertical and crosswise partial product generation is used to simplify the multiplication. Specifically:
• Q0 is generated by multiplying A0 and B0 (A0 × B0).
• Q1 is generated by crosswise multiplication and summing the partial products (A1 × B0 + A0 × B1).
• Q2 is generated by multiplying A1 and B1 (A1 × B1).
4. The resulting 4-bit product is produced by combining these partial products appropriately.
5. Finally, the product output (Q3 Q2 Q1 Q0) represents the multiplication result of A and B.
**Logic Gate Circuit Diagram**
**Layout and Waveform**
