https://github.com/soumyac1999/packet-classifier
Packet classifier of a router implemented in VHDL
https://github.com/soumyac1999/packet-classifier
Last synced: 10 months ago
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Packet classifier of a router implemented in VHDL
- Host: GitHub
- URL: https://github.com/soumyac1999/packet-classifier
- Owner: soumyac1999
- Created: 2019-05-03T07:44:41.000Z (over 6 years ago)
- Default Branch: master
- Last Pushed: 2019-05-30T05:37:58.000Z (over 6 years ago)
- Last Synced: 2024-12-30T21:41:43.408Z (12 months ago)
- Language: VHDL
- Homepage:
- Size: 4.87 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.txt
Awesome Lists containing this project
README
Project 5: Classify
Team: The Multiplexers
Team Code: E
Team Members:
Diwan Anuj Jitendra, 170070005
Soumya Chatterjee, 170070010
Arnab Jana, 170100082
Mohan Abhyas, 170260032
How to run the code:
1. Open Xilinx ISE and create a new project
using the standard chip settings used in the lab.
These are given for your reference in the instructions/ directory.
2. Click 'Add Source' by right-clicking the xc6slx45-2csg324
and import our 3 .vhd files. Make association of the testbench
as 'Simulation'.
3. Click 'New Source' and add a FIFO using IP CORE of Xilinx (please name the fifo as 'fifo') and
the settings shown in the screenshots in the instructions/ directory of this submission.
4. Simulate the testbench.