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https://github.com/soumyadip007/vhdl-modelsim-altera-simulator-coa
VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.
https://github.com/soumyadip007/vhdl-modelsim-altera-simulator-coa
computerarchitecture simulation vhdl-code
Last synced: about 1 month ago
JSON representation
VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.
- Host: GitHub
- URL: https://github.com/soumyadip007/vhdl-modelsim-altera-simulator-coa
- Owner: soumyadip007
- Created: 2019-04-17T18:27:18.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2019-12-01T07:55:14.000Z (about 5 years ago)
- Last Synced: 2024-10-12T06:18:51.373Z (2 months ago)
- Topics: computerarchitecture, simulation, vhdl-code
- Homepage:
- Size: 78.1 KB
- Stars: 4
- Watchers: 0
- Forks: 1
- Open Issues: 0