https://github.com/spcl/fblas
BLAS implementation for Intel FPGA
https://github.com/spcl/fblas
Last synced: 9 months ago
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BLAS implementation for Intel FPGA
- Host: GitHub
- URL: https://github.com/spcl/fblas
- Owner: spcl
- License: bsd-3-clause
- Created: 2019-02-07T14:43:22.000Z (almost 7 years ago)
- Default Branch: master
- Last Pushed: 2020-11-18T09:11:41.000Z (about 5 years ago)
- Last Synced: 2024-04-28T02:00:17.025Z (over 1 year ago)
- Language: C++
- Homepage:
- Size: 662 KB
- Stars: 76
- Watchers: 15
- Forks: 24
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# FBLAS
**FBLAS** is a porting of the BLAS numerical library ([http://www.netlib.org/blas/](http://www.netlib.org/blas/)) for Intel FPGA platform.
For more details, see our [paper](https://arxiv.org/abs/1907.07929).
## Code
### Requirements
The library depends on:
* Intel FPGA SDK for OpenCL pro, version 19+ ([http://fpgasoftware.intel.com/opencl/](http://fpgasoftware.intel.com/opencl/))
* GCC (version 5+)
* Rapidjson ([http://rapidjson.org/](http://rapidjson.org/))
* Google Test (only for unit tests)
* Python 3.6+
### Installation
After cloning this repository, make sure you clone the [rapidjson](http://rapidjson.org/) submodule dependency, by executing the following command:
```
git submodule update --init
pip install -r codegen/requirements.txt
```
## The FBLAS library
FBLAS provides two layers of abstraction:
* **HLS modules**, which can be integrated into existing hardware designs. They implement BLAS routines (`DOT`, `GEMV`, `GEMM`, etc.). Modules have been designed with compute performance in mind, exploiting the spatial parallelism and fast on-chip memory on FPGAs and have a streaming interface: data is received and produced using channels. In this way, they can be composed and communicate using on-chip resources rather than off-chip device RAM;
* a high-level **Host API** conforming to the classical BLAS interface that allows the user to invoke routines directly from a host program. No prior knowledge on FPGA architecture and/or tools is needed. The user writes a standard OpenCL program: she is responsible to transferring data to and from
the device, she can invoke the desired FBLAS routines working on the FPGA memory, and then she copies back the result from the device.
For further information on how to use the library, please refer to the [wiki](https://github.com/spcl/FBLAS/wiki).
## Publication
If you use FBLAS, please cite us:
```
@inproceedings{fblas,
author = {De Matteis, Tiziano and de Fine Licht, Johannes and Hoefler, Torsten},
title = {FBLAS: Streaming Linear Algebra on FPGA},
year = {2020},
isbn = {9781728199986},
publisher = {IEEE Press},
booktitle = {Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis},
articleno = {59},
numpages = {13},
keywords = {high level synthesis, spatial architectures, hardware library},
location = {Atlanta, Georgia},
series = {SC '20}
}
```
Concerning the Artifact Evaluation of the paper, you will find detailed information in subfolder `evaluation`.
## Contact
FBLAS can be used to build numerical applications, and be modified to include new features.
Contributions, comments, and issues are welcome!
## License
FBLAS is published under the New BSD license, see [LICENSE](LICENSE).