https://github.com/spcl/rivets
https://github.com/spcl/rivets
Last synced: 9 months ago
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- Host: GitHub
- URL: https://github.com/spcl/rivets
- Owner: spcl
- Created: 2023-05-08T13:34:06.000Z (over 2 years ago)
- Default Branch: master
- Last Pushed: 2023-06-18T10:41:11.000Z (over 2 years ago)
- Last Synced: 2025-02-10T00:57:55.587Z (11 months ago)
- Language: C
- Size: 85.9 KB
- Stars: 2
- Watchers: 7
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: readme.md
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README
# RIVETS: An Efficient Training and Inference Library for RISC-V with Snitch Extensions
### Quick start
Run simulation in banshee. Suitable for correctness checks but not cycle-accurate.
```
make banshee-dnn-matmul-8-64-32-32-matmul_raw_fp64_sdma_ssr_frep_omp-double-bench
make banshee-dnn-layernorm-64-64-layer_norm_raw_fp64_sdma_ssr_frep-double-bench
make banshee-dnn-abs-10000-eltwise_abs_raw_fp64_sdma_ssr_frep_omp-double-bench
```
Run simulation with verilator: cycle-accurate but slow.
```
make verilator-dnn-matmul-8-64-32-32-matmul_raw_fp64_sdma_ssr_frep_omp-double-bench
make verilator-dnn-layernorm-64-64-layer_norm_raw_fp64_sdma_ssr_frep-double-bench
make verilator-dnn-abs-10000-eltwise_abs_raw_fp64_sdma_ssr_frep_omp-double-bench
```