https://github.com/stavros/4bitcounterparload

A 4bit Counter with Parallel Load including a Clock Divider and a BCD decoder
https://github.com/stavros/4bitcounterparload

bcd counter fpga vhdl vhdl-code vhdl-examples

Last synced: about 6 hours ago
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A 4bit Counter with Parallel Load including a Clock Divider and a BCD decoder

• Host: GitHub
• URL: https://github.com/stavros/4bitcounterparload
• Owner: Stavros
• Created: 2020-02-03T17:43:52.000Z (almost 5 years ago)
• Default Branch: master
• Last Pushed: 2020-02-06T17:26:16.000Z (almost 5 years ago)
• Last Synced: 2024-11-17T07:15:47.497Z (2 months ago)
• Topics: bcd, counter, fpga, vhdl, vhdl-code, vhdl-examples
• Language: VHDL
• Size: 3.11 MB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# 4bitCounterParLoad

A 4bit Binary Counter with Parallel Load including a clock divider, a BCD decoder and a 7 segment display.

## Information

This is a VHDL project for DSD-I1* a Cyclone IV FPGA made in Quartus 18.1 and is based in the example of [pjbal](https://github.com/pjbal/DSD_LAB4).

**Diagram**:  

![Diagram](./4bitCounterParLoad.jpg)

**Behavioral VHDL code**: nbit_syncCount_parLoad.vhd  

**Testbench VHDL code**: nbit_syncCount_parLoad_tb.vhd  

**Modelsim**:  

![Modelsim](./4bitCounterParLoad_modelsim.jpg)

**FPGA**:  

![FPGA](./4bitCounterParLoad_fpga.jpg)

*Note: DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education [DOI:10.1109/DSD.2019.00032](https://ieeexplore.ieee.org/document/8875176)

## Licence

Copyright (c) 2019 Stavros Kalapothas (aka Stevaras) .

It is free software, and may be redistributed under the terms of the GNU Licence.