https://github.com/strikeless/strm1

STRM1 monorepo
https://github.com/strikeless/strm1

Last synced: 11 months ago
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STRM1 monorepo

• Host: GitHub
• URL: https://github.com/strikeless/strm1
• Owner: Strikeless
• Created: 2024-09-14T16:38:34.000Z (almost 2 years ago)
• Default Branch: lir_v2
• Last Pushed: 2025-07-08T19:04:22.000Z (12 months ago)
• Last Synced: 2025-07-08T20:23:13.930Z (12 months ago)
• Language: Rust
• Size: 230 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
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# STRM1

Very very **very** work in progress homebrew RISCy microprocessor architecture and codegen tooling.

This is a monorepo containing all the individual parts of the project.

Progress is slow, but maybe one day you can compile code through a custom compiler and run it on an FPGA implementation of the architecture. Just maybe, maybe not, we'll see.

## libstormir

libstormir is the most prominent and worked on thing here, it is/will be a compiler framework converting it's own intermediate representation language to machine code for the custom architecture.

The idea is similar to LLVM, just far simpler and worse.

I am aiming for libstormir to be target-extensible, allowing support for other targets with their own backends compiling IR to native code. Right now, this idea is far out of scope.

## The STRM1 architecture

As of writing, the architecture has nothing note-worthy, and only contains a few basic instructions. I'll develop the architecture further once libstormir can work with even these few basic instructions.