https://github.com/subbdue/systemverilog.io

Code used in
https://github.com/subbdue/systemverilog.io

Last synced: 3 months ago
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Code used in

• Host: GitHub
• URL: https://github.com/subbdue/systemverilog.io
• Owner: subbdue
• Created: 2016-10-12T06:01:55.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2017-06-25T18:04:50.000Z (over 7 years ago)
• Last Synced: 2024-08-03T01:39:30.017Z (6 months ago)
• Language: SystemVerilog
• Homepage: https://systemverilog.io
• Size: 1010 KB
• Stars: 161
• Watchers: 18
• Forks: 28
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# systemverilog.io

## Introduction

Welcome to systemverilog.io. You'll find all the code used in https://systemverilog.io here.

General notes:

* The table of contents below specifies which article a directory belongs to.

* Each directory has a `readme.md` which has instructions to run the examples

* You'll also find instructions to run an example at the head of the `.sv` file. For example checkout the head of `random-number-generation/prng1.sv`

## Table of Contents

1. `macros`:  [SystemVerilog Macros](https://systemverilog.io/macros.html)

2. `random-number-generation`:  [SystemVerilog Randomization & Random Number Generation](https://systemverilog.io/randomization.html)

3. `random-stability`:  [SystemVerilog Random Stability](https://systemverilog.io/random-stability.html)

4. `vmc-swift`: [How to Create & Use VMC SWIFT Models](https://systemverilog.io/vmc-swift.html)

5. `generate`: [SystemVerilog Generate Construct](https://systemverilog.io/generate.html)