https://github.com/sudhamshu091/32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
https://github.com/sudhamshu091/32-Verilog-Mini-Projects

miniproject verilog verilog-hdl verilog-project

Last synced: 3 months ago
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Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

• Host: GitHub
• URL: https://github.com/sudhamshu091/32-Verilog-Mini-Projects
• Owner: sudhamshu091
• License: other
• Created: 2020-12-02T16:15:32.000Z (about 4 years ago)
• Default Branch: main
• Last Pushed: 2022-07-17T17:45:03.000Z (over 2 years ago)
• Last Synced: 2024-05-20T03:14:01.926Z (8 months ago)
• Topics: miniproject, verilog, verilog-hdl, verilog-project
• Language: Verilog
• Homepage:
• Size: 12.6 MB
• Stars: 470
• Watchers: 8
• Forks: 95
• Open Issues: 1
• Metadata Files:
  • Readme: README.md

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