https://github.com/sunzey/cpu_project

recording codes of CPU under mips ISA in lecture of computer organization
https://github.com/sunzey/cpu_project

buaa buaa-co cpu learning verilog

Last synced: 21 days ago
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recording codes of CPU under mips ISA in lecture of computer organization

• Host: GitHub
• URL: https://github.com/sunzey/cpu_project
• Owner: SunzeY
• License: mit
• Created: 2021-01-02T04:01:31.000Z (about 4 years ago)
• Default Branch: P7
• Last Pushed: 2021-08-24T05:38:00.000Z (over 3 years ago)
• Last Synced: 2024-11-15T12:33:49.487Z (3 months ago)
• Topics: buaa, buaa-co, cpu, learning, verilog
• Language: Verilog
• Homepage:
• Size: 2.17 MB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# CPU_project

recording codes of CPU under mips ISA in lecture of computer organization in BUAA2020  

here is a brief introduction of each branch:  

`Project number`: `content` (`base_stage`)  

**P0**: digital circuits (Logism)  

**P1**: digital circuits focus on state-machine (Verilog)  

**P2**: mips assembly language (Mars)  

**P3**: Single cycle CPU with 9 mips commands (Logism)  

**P4**: Single cycle CPU with 9 mips commands (Verilog)  

**P5**: Pipelined CPU with 11 mips commands (Verilog)  

**P6**: Pipelined CPU with 52 mips commands (Verilog)  

**P7**: Pipelined CPU with interrupt/exception handling supported (Verilog)