https://github.com/susiejojo/mips_processor

A simple MIPS processor implemented using Verilog capable of supporting basic I,J and R type instructions. Built using Xilinx Vivado 2019.1
https://github.com/susiejojo/mips_processor

mips mips-architecture processor verilog

Last synced: about 1 month ago
JSON representation

A simple MIPS processor implemented using Verilog capable of supporting basic I,J and R type instructions. Built using Xilinx Vivado 2019.1

• Host: GitHub
• URL: https://github.com/susiejojo/mips_processor
• Owner: susiejojo
• Created: 2020-03-11T20:26:04.000Z (almost 5 years ago)
• Default Branch: master
• Last Pushed: 2020-05-20T12:17:04.000Z (over 4 years ago)
• Last Synced: 2024-04-14T12:22:17.236Z (9 months ago)
• Topics: mips, mips-architecture, processor, verilog
• Language: Verilog
• Homepage:
• Size: 166 KB
• Stars: 4
• Watchers: 1
• Forks: 1
• Open Issues: 0

Awesome Lists containing this project