https://github.com/swetland/gateware

A collection of little open source FPGA hobby projects
https://github.com/swetland/gateware

ecp5 fpga gateware ice40 systemverilog

Last synced: 4 months ago
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A collection of little open source FPGA hobby projects

• Host: GitHub
• URL: https://github.com/swetland/gateware
• Owner: swetland
• Created: 2015-12-27T12:30:17.000Z (over 10 years ago)
• Default Branch: master
• Last Pushed: 2020-02-06T23:16:53.000Z (over 6 years ago)
• Last Synced: 2025-03-10T18:52:20.530Z (over 1 year ago)
• Topics: ecp5, fpga, gateware, ice40, systemverilog
• Language: SystemVerilog
• Homepage:
• Size: 257 KB
• Stars: 48
• Watchers: 7
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README

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README

          

This is a collection of little open source FPGA hobby projects

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The build system can target nextpnr-ice40, nextpnr-ecp5, (Lattice

ICE40 and ECP5 family parts), verilator (simulation), and vivado

(Xilinx parts).

Projects are defined in project/*.def and all buildable projects

can be listed with "make" and built with "make " or

"make all"

Final build products are deposited in out/... and intermediate

build products, logs, and so on, in out/-nextpnr-/{projectname}/...,

out/-vsim-/{projectname}/..., etc.