https://github.com/taffarel55/verilog

Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.
https://github.com/taffarel55/verilog

verilog verilog-examples verilog-hdl

Last synced: about 19 hours ago
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Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.

• Host: GitHub
• URL: https://github.com/taffarel55/verilog
• Owner: taffarel55
• Created: 2020-11-02T17:46:03.000Z (about 4 years ago)
• Default Branch: main
• Last Pushed: 2023-08-05T22:34:16.000Z (over 1 year ago)
• Last Synced: 2024-11-11T06:17:17.022Z (about 2 months ago)
• Topics: verilog, verilog-examples, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 35.2 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0

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