https://github.com/tahirzia-1/digital-clock-verilog
This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.
https://github.com/tahirzia-1/digital-clock-verilog
7segment digitalclock fpga fpga-programming fpga-soc nexys4ddr simulation synthesis systemverilog systemverilog-hdl verilog verilog-hdl vivado vivado-simulator
Last synced: about 2 months ago
JSON representation
This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.
- Host: GitHub
- URL: https://github.com/tahirzia-1/digital-clock-verilog
- Owner: TahirZia-1
- Created: 2025-02-28T22:38:25.000Z (about 2 months ago)
- Default Branch: main
- Last Pushed: 2025-02-28T23:42:39.000Z (about 2 months ago)
- Last Synced: 2025-03-01T00:35:03.218Z (about 2 months ago)
- Topics: 7segment, digitalclock, fpga, fpga-programming, fpga-soc, nexys4ddr, simulation, synthesis, systemverilog, systemverilog-hdl, verilog, verilog-hdl, vivado, vivado-simulator
- Language: Tcl
- Homepage:
- Size: 166 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0