https://github.com/taichi-ishitani/tnoc

Network on Chip Implementation written in SytemVerilog
https://github.com/taichi-ishitani/tnoc

amba amba-axi axi axi4 network-on-chip noc systemverilog uvm

Last synced: 5 days ago
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Network on Chip Implementation written in SytemVerilog

• Host: GitHub
• URL: https://github.com/taichi-ishitani/tnoc
• Owner: taichi-ishitani
• License: apache-2.0
• Created: 2017-12-12T14:43:45.000Z (about 7 years ago)
• Default Branch: master
• Last Pushed: 2022-08-27T14:30:51.000Z (over 2 years ago)
• Last Synced: 2024-12-11T13:28:57.259Z (11 days ago)
• Topics: amba, amba-axi, axi, axi4, network-on-chip, noc, systemverilog, uvm
• Language: SystemVerilog
• Homepage:
• Size: 406 KB
• Stars: 159
• Watchers: 13
• Forks: 44
• Open Issues: 5
• Metadata Files:
  • Readme: README.md
  • Funding: .github/FUNDING.yml
  • License: LICENSE

Awesome Lists containing this project

• awesome-opensource-hardware - tnoc

README

        
# Network on Chip Implementation Written in SystemVerilog

## Overview

This is a Network on Chip (NoC) Router/Fabric implementation written in SystemVerilog. It has following features.

* 2-D mesh network

* Dimension order routing (X-Y routing)

* Flow control

    * Wormhole (FLIT based) flow control

    * Virtual channel flow control

    * On/Off Flow control

* Configurable design

    * Packet format

    * Mesh size

    * FIFO size

    * etc.

* Support standard bus protocol

    * AMBA AXI4

## Details

TBW

## Contact

If you have any problems, questions, ideas, etc., you can post them on the following ways.

1. [Issue Tracker](https://github.com/taichi-ishitani/noc/issues/new)

2. [Chat Room](https://gitter.im/taichi-ishitani/noc)

3. [Mail](mailto:[email protected])

## Copyright

Copyright (c) 2017-2018 Taichi Ishitani. See [LICENSE](LICENSE) for further details.