https://github.com/tariqjamel/image-processing-in-verilog
An image processing pipeline written in Verilog that performs RAW Bayer to RGB conversion and applies 3x3 convolution filters like blur and identity for pixel-level image enhancement.
https://github.com/tariqjamel/image-processing-in-verilog
image-processing modelsim pipeline pixel-processing rgb verilog vhdl xilinx xilinx-fpga
Last synced: 5 months ago
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An image processing pipeline written in Verilog that performs RAW Bayer to RGB conversion and applies 3x3 convolution filters like blur and identity for pixel-level image enhancement.
- Host: GitHub
- URL: https://github.com/tariqjamel/image-processing-in-verilog
- Owner: tariqjamel
- Created: 2025-07-08T18:43:17.000Z (12 months ago)
- Default Branch: main
- Last Pushed: 2025-07-08T18:52:33.000Z (12 months ago)
- Last Synced: 2025-07-19T22:59:56.301Z (11 months ago)
- Topics: image-processing, modelsim, pipeline, pixel-processing, rgb, verilog, vhdl, xilinx, xilinx-fpga
- Language: Verilog
- Homepage:
- Size: 62.5 KB
- Stars: 1
- Watchers: 0
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# 🎞️ Verilog Image Processing Pipeline
This project implements a basic **image processing pipeline** in Verilog. It performs:
- ✅ Bayer-pattern RAW to RGB conversion (`raw2rgb`)
- ✅ 3x3 convolution filtering (`img_filter`)
- ✅ Integration into a complete pipeline (`pixel_pipeline`)
- ✅ Testbench for verification (`tb_pixel_pipeline`)
## Screenshot
## 📌 Features
### 🔸 RAW to RGB (Demosaicing)
- Supports `RGGB` Bayer pattern
- Line-buffer based approach for streaming pixel input
- Generates valid RGB once a 2x2 neighborhood is filled
### 🔸 Image Filter
- Applies 3x3 convolution filters on RGB data
- Supported filters:
- `00`: Identity
- `01`: Blur
- Uses sliding window with shift registers
### 🔸 Pipeline Integration
- Top-level `pixel_pipeline` connects `raw2rgb` → `img_filter`
- Parameterized sensor pattern and filter type
### 🔸 Testbench
- Provides a 2x2 RAW input image:
- R G
- G B