https://github.com/taunusflieger/esp32s3-ulp-experiment

https://github.com/taunusflieger/esp32s3-ulp-experiment

Last synced: about 2 months ago
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• Host: GitHub
• URL: https://github.com/taunusflieger/esp32s3-ulp-experiment
• Owner: taunusflieger
• License: apache-2.0
• Created: 2023-02-12T08:06:52.000Z (almost 2 years ago)
• Default Branch: master
• Last Pushed: 2023-02-12T08:41:41.000Z (almost 2 years ago)
• Last Synced: 2024-01-06T14:41:00.101Z (12 months ago)
• Language: Rust
• Size: 12.7 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE-APACHE

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README

        
# ESP32-S3 ULP Experiment

This experiment demonstrates the interaction between the Xtensa main cores and the RiscV ULP core.

There are two seperate programs one for the Xtensa core and one for the RiscV core. Both have a seperate build process and linked to together into one executable. First the esp32-ulp-blink (RiscV)needs to be compiled and than the esp-ulp-test (Xtensa).