https://github.com/tcr/rust-verilog

Verilog parsing and generator crate.
https://github.com/tcr/rust-verilog

Last synced: 19 days ago
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Verilog parsing and generator crate.

• Host: GitHub
• URL: https://github.com/tcr/rust-verilog
• Owner: tcr
• Created: 2017-01-09T06:29:55.000Z (about 8 years ago)
• Default Branch: master
• Last Pushed: 2020-04-16T01:46:24.000Z (almost 5 years ago)
• Last Synced: 2024-12-27T18:38:16.479Z (24 days ago)
• Language: Rust
• Homepage:
• Size: 277 KB
• Stars: 20
• Watchers: 2
• Forks: 2
• Open Issues: 2
• Metadata Files:
  • Readme: README.md

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README

        
# rust-verilog

```

[dependencies]

verilog = "0.0.1"

```

Parses and generates Verilog code.

```rust

extern crate verilog;

let code: verilog::ast::Code = verilog::parse("module a(); endmodule");

```

## License

MIT or Apache-2.0, at your option.