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https://github.com/tcr/rust-verilog
Verilog parsing and generator crate.
https://github.com/tcr/rust-verilog
Last synced: 2 months ago
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Verilog parsing and generator crate.
- Host: GitHub
- URL: https://github.com/tcr/rust-verilog
- Owner: tcr
- Created: 2017-01-09T06:29:55.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2020-04-16T01:46:24.000Z (over 4 years ago)
- Last Synced: 2024-07-04T01:59:44.489Z (3 months ago)
- Language: Rust
- Homepage:
- Size: 277 KB
- Stars: 20
- Watchers: 2
- Forks: 2
- Open Issues: 1
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Metadata Files:
- Readme: README.md
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README
# rust-verilog
```
[dependencies]
verilog = "0.0.1"
```Parses and generates Verilog code.
```rust
extern crate verilog;let code: verilog::ast::Code = verilog::parse("module a(); endmodule");
```## License
MIT or Apache-2.0, at your option.