https://github.com/teewrath/arithematic-logic-unit

Arithematic Logical Unit written in Verilog
https://github.com/teewrath/arithematic-logic-unit

Last synced: 6 months ago
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Arithematic Logical Unit written in Verilog

• Host: GitHub
• URL: https://github.com/teewrath/arithematic-logic-unit
• Owner: TeeWrath
• Created: 2023-11-26T20:59:26.000Z (over 2 years ago)
• Default Branch: master
• Last Pushed: 2023-11-26T21:13:24.000Z (over 2 years ago)
• Last Synced: 2025-02-09T12:31:45.276Z (over 1 year ago)
• Language: Verilog
• Homepage:
• Size: 1.95 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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# Arithematic-Logic-Unit

Repository containing logic for ALU in Verilog