https://github.com/thedhruvrawat/comparch

This repository contains all the laboratory coursework for the course CS F342: Computer Architechture at BITS Pilani, Pilani Campus (Fall '22)
https://github.com/thedhruvrawat/comparch

computer-architecture verilog

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This repository contains all the laboratory coursework for the course CS F342: Computer Architechture at BITS Pilani, Pilani Campus (Fall '22)

• Host: GitHub
• URL: https://github.com/thedhruvrawat/comparch
• Owner: thedhruvrawat
• Created: 2022-09-03T06:34:59.000Z (over 2 years ago)
• Default Branch: master
• Last Pushed: 2023-01-01T11:50:42.000Z (about 2 years ago)
• Last Synced: 2024-11-09T08:40:52.313Z (2 months ago)
• Topics: computer-architecture, verilog
• Language: Verilog
• Homepage:
• Size: 1.88 MB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
## CS F342: Computer Architechture

![Language](https://img.shields.io/static/v1?label=Language&message=Verilog&color=informational&style=for-the-badge)

This repository contains all the laboratory coursework for the course **CS F342: Computer Architechture** at BITS Pilani, Pilani Campus in Fall 2022.

### Lab Summary

| Lab | Topic | Lab Sheet | Date |

| ------------- | ------------- | --- | -- |

| 1  | Getting started with Icarus Simulator, basic Verilog language primitives, types of modelling | [Lab 1](lab-01/labsheet.pdf) | 17 Sep 2022 |

| 2  | Combinational Digital Circuit Modelling, `4x1` Mux, `3x8` decoder, Full Adder/Subtractor | [Lab 2](lab-02/labsheet.pdf) | 24 Sep 2022 |

| 3  | Sequential circuits, blocking and non-blocking assignments, Finite State Machine, 4-bit Shift Register | [Lab 3](lab-03/labsheet.pdf) | 01 Oct 2022 |

| 4  | Design a simple MIPS ALU, control PLA and ALU control logic | [Lab 4](lab-04/labsheet.pdf) | 08 Oct 2022 |

| 5  | Designing a sample 32-bit register file for a MIPS processor | [Lab 5](lab-05/labsheet.pdf) | 15 Oct 2022 |

| 6  | Modeling MIPS Single Cycle Datapath in Verilog | [Lab 6](lab-06/labsheet.pdf) | 22 Oct 2022 |

| 7  | Modeling 3-stage pipeline design in Verilog | [Lab 7](lab-07/labsheet.pdf) | 12 Nov 2022 |

> These solutions have been put up only for reference. Do not copy and submit this code. The course involves strict plagiarism check, and I am not liable for any loss of marks to you. Code under **MIT License**.