https://github.com/thedhruvrawat/dd

Repository for lab component of the course CS F215: Digital Design at BITS Pilani, Pilani campus (Fall '21)
https://github.com/thedhruvrawat/dd

digital-design digital-logic logisim

Last synced: 14 days ago
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Repository for lab component of the course CS F215: Digital Design at BITS Pilani, Pilani campus (Fall '21)

• Host: GitHub
• URL: https://github.com/thedhruvrawat/dd
• Owner: thedhruvrawat
• License: mit
• Created: 2021-08-20T12:50:49.000Z (over 3 years ago)
• Default Branch: master
• Last Pushed: 2021-12-05T13:21:25.000Z (about 3 years ago)
• Last Synced: 2024-11-09T08:40:50.323Z (2 months ago)
• Topics: digital-design, digital-logic, logisim
• Homepage:
• Size: 6.61 MB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
## CS F215: Digital Design Lab

![Platform](https://img.shields.io/static/v1?label=Platform&message=Logisim&color=informational&style=for-the-badge)

This repository contains all the laboratory coursework for the course **CS F215: Digital Design** at BITS Pilani, Pilani Campus in Fall 2021.

### Instructions to view

1. Open [Logisim](./logisim.exe) 

2. Go to FILE -> OPEN and open the required `.circ` file to see the circuit.

### Brief Summary

| Lab | Date | Topic | Link |

| ------------- | ------------- | --- | --|

| 0  | 25 August 2021  | Introduction to [**Logisim**](http://www.cburch.com/logisim/) | [Lab 0](./lab-00) |

| 1  | 4 September 2021  | Realize **canonical SOP form** and **POS form** of the given Boolean function | [Lab 1](./lab-01) |

| 2  | 11 September 2021  | Design a **BCD to Excess-3** code converter circuit | [Lab 2](./lab-02) |

| 3  | 18 September 2021  | 1. Design a **4-bit binary adder** which is also capable of handling substraction 
 2. Design a **Full Substractor** using Half Substractor blocks | [Lab 3](./lab-03) |

| 4  | 25 September 2021  | Design a **BCD to 7 segment decoder** | [Lab 4](./lab-04) |

| 5  | 9 October 2021  | Design a **4-bit magnitude comparator** | [Lab 5](./lab-05) |

| 6  | 16 October 2021  | Design a **4:1 multiplexer** using 
1. Only *CMOS* 
 2. Only *Transmission Gates (TG)* and *NOT* gates | [Lab 6](./lab-06) |

| 7  | 23 October 2021  | 1. Design a **T flip-flop** using JK flip-flops 
 2. Design a **JK flip-flop** using T flip-flops | [Lab 7](./lab-07) |

| 8  | 13 November 2021  | Design a Sequence Detector **Mealy machine** with T flip-flop | [Lab 8](./lab-08) |

| 9  | 20 November 2021  | Design a **Universal Shift Register** | [Lab 9](./lab-09) |

| 10  | 27 November 2021  | Design a 3-bit synchronous **binary UP/DOWN counter** | [Lab 10](./lab-10) |