https://github.com/thomastrain00/esoc-iii

DeVry eSOC III FPGA Dev Board (Altera Cyclone III EP3C16Q240C8)
https://github.com/thomastrain00/esoc-iii

Last synced: about 2 months ago
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DeVry eSOC III FPGA Dev Board (Altera Cyclone III EP3C16Q240C8)

• Host: GitHub
• URL: https://github.com/thomastrain00/esoc-iii
• Owner: thomastrain00
• Created: 2022-03-30T01:13:23.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2022-04-01T01:36:13.000Z (over 2 years ago)
• Last Synced: 2023-10-07T08:29:02.352Z (about 1 year ago)
• Language: HTML
• Homepage:
• Size: 9.89 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# eSOC-III

Collection of my projects and docs for the DeVry eSOC III FPGA Dev Board (Altera Cyclone III EP3C16Q240C8).

![DeVry eSOC III FPGA Dev Board (Altera Cyclone III EP3C16Q240C8)](imgs/top_board.jpg)

## Projects:

1. Blink LED

    * Toggles green LED labeled "GN8".

    * Uses a counter to count number of clock cycles. Time is based on 24 MHz clock.

2. 4-bit ALU

    * ALU calculates sum, product, remainder, and bitwise AND of two 4-bit inputs.

    * Inputs represented in binary using DIP switches

    * 8 green LEDs represent 8-bit ALU result  

3. Clock Divider 

    * TODO

## Setup

* TODO

---

## Helpful resources

1. [FPGA Tutorial: Blink an LED (Video)](https://youtu.be/Qd01NJi1AnY)

    * Quick intro to Quartus II workflow and getting code onto FPGA

2. [Learning Verilog for FPGA Development (Paid LinkedIn Learning Course)](https://www.linkedin.com/learning/learning-verilog-for-fpga-development)

    * Short and concise intro to Verilog HDL with a few challenges. About a 2-3 hours to complete.

    * Paid course but I got free access through a promotion from LinkedIn.