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https://github.com/thoughtpolice/yosys-bluespec

Yosys plugin for synthesis of Bluespec code
https://github.com/thoughtpolice/yosys-bluespec

bluespec fpga

Last synced: about 2 months ago
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Yosys plugin for synthesis of Bluespec code

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README 

        



# Bluespec integration for Yosys



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  Yosys HQ  •  Bluespec




---






This is a plugin for **[Yosys]** that allows you to easily integrate

**[Bluespec]** code into your Yosys-based synthesis flows and tools. It uses

the Bluespec compiler (`bsc`) to compile your designs to Verilog, and then

ingests the results.



> **NOTE**: Although it should go without saying, this plugin **doesn't**

> attempt to assist you with simulation using Bluesim/Icarus/Verilator, etc. It

> is only meant to assist in actual HDL synthesis.



[Yosys]: https://github.com/yosyshq/yosys

[Bluespec]: https://github.com/B-Lang-org/bsc



## Installation



Just run `make install`. The `Makefile` will use `yosys-config` to determine

how to link and compile the plugin, and install it in the Yosys data directory.

You can specify the `yosys-config` binary to use by running `make

YOSYS_CONFIG=foo`.  By default the Makefile uses whatever is in `$PATH`.



If Yosys is installed globally, you'll need to use `sudo` with the `install`

target. The `install` target supports `PREFIX=` and `DESTDIR=` so you can

control the installation paths as you expect.



## Usage



Run `plugin -i bluespec` once you've dropped inside `yosys`. This gives you the

`read_bluespec` command.



Run `help read_bluespec` inside Yosys for detailed information.



## Quick Example



Given you have some BlueSpec package `Foo.bsv`, with a top-level module you

want to synthesize called `mkFoo`, you can spit out a "prepped" Verilog file as

follows (using escaped strings in Bash):



```bash

$ yosys -p "\

plugin -i bluespec;

read_bluespec -top mkFoo Foo.bsv;

prep;

write_verilog -attr2comment out.v;

"

```



> **NOTE**: The `read_bluespec` command only supports the SystemVerilog flavor

> of Bluespec. Haskell support will be added in the future.



The resulting `out.v` file will contain your Verilog output. This file is

standalone and does not depend on BSV or BSV Verilog primitives at all, and

should work in a verification/synthesis toolchain.



The compiled `Foo.bsv` module will have all of its dependencies automatically

compiled as well. All BlueSpec modules that have been marked `(* synthesize *)`

to emit Verilog output will be incorporated into the resulting Verilog design.



The `read_bluespec` command always fully recompiles its input files, so it may

not be appropriate for fast development iteration, only for true

synthesis/integration runs through your toolchain.



## Module resolution



The `bluespec` plugin attempts to automatically resolves modules for BSV

primitives written in Verilog. For example, using the `FIFO::*` package in BSV

and compiling to Verilog results in a module that depends on `FIFO2.v`, located

in `$BLUESPECDIR/Verilog/FIFO2.v`. This module will be loaded automatically.



This feature is on by default, which makes it relatively easy to incorporate

custom BlueSpec designs into Yosys quickly. See `help read_bluespec` for more

information on this feature and how to turn it off for more advanced use cases.



## Future work



This plugin is currently very primitive, and can only be used to synthesize

designs for straight-forward use cases. That said, it should probably work fine

with FOSS EDA tools. Please feel free to submit ideas or improvements.



Now that Bluespec is open source, future work might revolve around improved

integration with `bluetcl` or somesuch.



## License



ISC License, the same as Yosys. See `LICENSE.txt` for the exact terms of

copyright and redistribution.