https://github.com/tiesen243/learn-hdl
https://github.com/tiesen243/learn-hdl
Last synced: about 1 year ago
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- Host: GitHub
- URL: https://github.com/tiesen243/learn-hdl
- Owner: tiesen243
- License: mit
- Created: 2024-10-16T16:08:26.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2025-03-14T15:50:36.000Z (about 1 year ago)
- Last Synced: 2025-03-14T16:39:32.024Z (about 1 year ago)
- Language: Verilog
- Size: 42 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# Verilog HDL Project
This repository contains the Verilog Hardware Description Language (HDL) source code and supporting files for designing an integrated circuit (IC) that implements [brief description of IC functionality].
## Getting Started
### Prerequisites:
- Verilog simulator (ModelSim)
- Synthesis tool (Intel Quartus)
### Setup:
- Clone or download the repository.
- Install the required tools and software, following their respective installation guides.
- Open Quartus
## License
This project is licensed under the [MIT]. See the [LICENSE](LICENSE) file for details.